The present invention relates to measurement and analysis of electronic logic circuits and, more particularly, to a logic state transition sensor circuit.
A fundamental means of reducing power dissipation within a digital logic system, such as within a micro-processing system, is to reduce an amount of logic state transitions that occur during execution of arbitrary operations. A logic state transition is typically an operation, which occurs when an electrical signal with a voltage that represents a logic value changes to a different voltage that represents a different logic value.
In ideal circumstances, the definitive nature of Boolean operations permits an exact determination of the amount of logic state transitions that can occur at a particular electrical node of a circuit in response to known logic inputs to the circuit. The situation is complicated though, by injection of random uncontrollable operations and/or logic inputs, which occurs during normal processing within the circuit. This prevents the possibility of a known specification of outputs or logic state transition activity within the circuit. The situation is further complicated by an extremely large number of electrical nodes (or logic gates) within typical circuits, as within state-of-the-art integrated circuits, which makes a thorough analysis of actual logic state transitions that occur at each constituent gate or electrical node of an integrated circuit very impractical.
Simulations using statistical methods can also produce estimations of logic transition activity at a particular electrical node of a circuit. However, simulations also may not be able to determine actual logic transition activity resulting from random operations and inputs that occur during normal operation, since simulations cannot precisely predict when a random input will occur.
Also, to reduce the complexity of simulations, algorithms, or statistical methods, logic signals are commonly modeled as either delay-free signals or with nominal delay timing. The timing may be calculated and estimated based on a nominal implementation of the logic circuit as that compared to an integrated circuit. However, actual logic signals are subject to timing uncertainty due to uncontrollable circumstances such as random variations in the integrated circuit processing, disturbances in supply voltage, temperature changes, as well as many others. The cumulative effect of these variations can lead to momentary incorrect logic state transitions known as glitches. Since pure simulation or statistical methods cannot account for these random variations, simulation and statistical analysis procedures cannot accurately model or predict when a glitch will occur within a circuit.
Consequently, simulations and statistical methods for estimating logic state transition activity within a circuit are limited by unrealistic assumptions of delay-free or fixed-delay logic signals, a lack of ability to model random variations in logic signal timing, and an inability to perform a thorough analysis of complex circuitry under arbitrary combinations of operations and logic inputs to the circuit. Even if logic state transition activity can be accurately predicted (or closely predicted) by a simulation, it may be impractical to use simulation data when a measurement of the activity may be desired in real-time. Therefore, it is desirable to overcome these problems.
Generally speaking, the present invention may permit a direct, real-time measurement of logic state transition activity at an electrical node. As such, measurements of logic state transitions may not be limited by assumptions made from using simulation or statistical methods.
In an exemplary embodiment, a logic state transition sensor circuit is provided. The logic state transition sensor circuit may comprise a sensing circuit coupled to an electrical node and a recording circuit coupled to the sensing circuit. The sensing circuit may generate a pulse in response to a logic state transition at the electrical node. In turn, the recording circuit may accumulate a capacitive charge in response to each pulse generated by the sensing circuit. The accumulated capacitive charge may be representative of a number of logic state transitions sensed at the electrical node.
In another respect, the sensing circuit may generate a momentary output signal in response to a logic state transition at the electrical node. The recording circuit may be able to keep count of each momentary output signal generated by the sensing circuit. The recording circuit may output an output signal representative of a number of logic state transitions sensed at the electrical node.
In still another respect, the exemplary embodiment may take the form of a method of sensing logic state transitions. The method may include generating a momentary signal in response to a logic state transition at an electrical node. The method may also include accumulating a capacitive charge in response to each momentary signal generated. The method may further include outputting an output signal representative of a number of logic state transitions sensed at the electrical node.
These as well as other features and advantages will become apparent to those of ordinary skill in the art by reading the following detailed description, with appropriate reference to the accompanying drawings.